1. Field of the Invention
The invention relates to a method of, and apparatus for, refreshing semiconductor memory.
2. Discussion of the Related Art
Two of the most common types of RAM cells are static random access memory (SRAM) and dynamic random access memory (DRAM). SRAM cells have a static latching structure that can indefinitely store data so long as power is applied. DRAM cells have storage nodes comprising capacitors and transistors. DRAM cells store data by holding a charge in the capacitors.
Because electric charge leaks out of all capacitors, it is regarded as a characteristic of DRAM that data cannot be stored permanently. The charged storing nodes discharge, therefore DRAM cells need periodic xe2x80x9crefreshingxe2x80x9d with a new electric charge. The aforementioned periodic refreshing operations are generally performed to each cell a number of times per second to prevent loss of data.
A refresh circuit is used to perform the DRAM refreshing operations. Early DRAMs performed the refresh operations under the control of an external memory device. Recently, most DRAM devices have an internal logic circuit combined with the refresh circuit to perform xe2x80x9cinternal refreshing operations.xe2x80x9d Conventionally, internally refreshing DRAM devices have different external operation conditions from those for SRAMs. Specifically, internally refreshing DRAMs should satisfy at least one of two external operation conditions, (1) a definite write restoration time to be added to the last part of every write cycle and (2) a maximum write cycle time, neither of which are needed for SRAM. An elapsing write restoration time makes the DRAM write access time slower than regular read access time, and a maximum write cycle time imposes a maximum limit to the length of an external write cycle, both conditions imposed to prevent loss of data before refresh.
Despite the refresh requirements, there are a number of advantages that DRAMs have over SRAMs. Among them, DRAM cells are smaller than SRAM cells produced by similar fabricating processes. Reduction of memory cell size reduces production costs while providing larger data storage capacity. Thus, it is preferable to develop DRAMs that can replace SRAMs without imposing additional external operational conditions.
U.S. Pat. No. 4,984,208, issued on Jun. 12, 1989, entitled xe2x80x9cDynamic Read/Write Memory Device Having Better Refresh Operationsxe2x80x9d discloses a DRAM circuit that can satisfy conditions of write restoration time and maximum cycle time.
An array layout structure of DRAM cells of a conventional DRAM device accessing in a partial word line activation method was disclosed by Takahashi and others in U.S. Pat. No. 6,031,779, issued Feb. 29, 2000, wherein sub-arrays of the memory cells are surrounded with block sense amplifier arrays and sub-word line driver arrays.
FIG. 1 shows a general layout of a refresh-type semiconductor memory device layout as commonly used in the art and as may be used in this invention, if desired. A plurality of memory cell array blocks 40 are divided into n number of row blocks and m number of column blocks, and a plurality of memory sense amplifiers 30 are arranged between the cell array blocks 40 in the direction of rows or bit lines. The block sense amplifiers 30 are shared by two memory cell array blocks 40, but not for those arranged at both ends of the memory cell array blocks 40. In the direction of word lines or columns, sub-word line drivers SWD 20 are arranged between the memory cell array blocks 40 in the structure such that two memory cell array blocks 40 share one sub-word line driver 20. Even though not shown in FIG. 1, row and column decoders are arranged in the row and column directions. The row and column decoders designate addresses for specific memory cells.
In the layout structure shown in FIG. 1, those block sense amplifiers 30 and sub-word line drivers 20 disposed at the periphery of the layout are not shared, but rather connected only with one memory cell array block 40. In FIG. 1, there are portions of the array where areas accommodating the block sense amplifiers 30 and sub-word line drivers 20 are crossed. The crossed areas are called conjunction areas 50. Drivers (not shown) are disposed in the conjunction areas 50 to drive the block sense amplifiers 30.
In the layout structure, after a bit line BL is precharged, a normal word line enable signal NWE and an address coding LSB signal PXi are transmitted to selectively activate one of word lines arranged in the column direction of the array. Then, the selected word line turns on access transistors of the memory cells connected thereto, so as to allow a storing node of each memory cell and a specific bit line connected to the memory cell to share the charge. As a result, the block sense amplifiers 30 sense the activated bit line and then store the sensed data with internal latches. The stored data is passed to an input/output line when a column select line CSL is enabled in response to a column address decoding signal. In this case, if data is not passed to the input/output line because the column select line CSL is not enabled, the data is re-written to a corresponding memory cell during an active restoration process, and a refresh operation is performed while the word line is activated.
In a general architecture of a DRAM device, all memory cells connected to word lines to be enabled can share the electric charge regardless of active restoration or refresh operation. The drivers of the conjunction area 50 (hereinafter, xe2x80x9cLA driversxe2x80x9d) should be driven in advance to facilitate data sensing by the block sense amplifiers 30 connected to bit lines of the selected memory cell array blocks. This process requires comparatively large amounts of power. Conventional methods to reduce such power consumption include partial word line activation wherein only a minimum number of word lines and LA drivers are enabled and driven. In other words, column block information signals decoded by column addresses are mixed to enable only word lines corresponding to a memory cell array block 40 whose column select line CSL opens and to drive only a LA driver corresponding to the memory cell array block 40.
However, there have been problems in application of the partial word line activation method to the DRAM architecture. For example, two memory cell array blocks may share a new charge when a word line is enabled. This is because a SWD array 20 is shared by two memory cell array blocks 40 for purposes of minimizing the size of the DRAM device.
Besides, the other problem is that it is difficult to drive only a LA driver to drive a block sense amplifier commonly connected to two block bit lines because the partial word line activation method accesses in the structure where sub-word line driver 20 and block sense amplifier 30 are shared by memory cell array blocks. In other words, if an output signal ORed by a column block address decoded signal, for instance, a block selection Y (BSY) signal, controls circuits of conjunction areas, only word lines related to the two cell array blocks are activated to drive only a corresponding LA driver that receives an OR output signal, but not other LA drivers of the conjunction areas positioned over and under the driven driver. At this time, there is no problem in the sensing or active restoration process, but at the price of a significant reduction in the total driving capacity of the block sense amplifiers 30. Consider the situation wherein all block sense amplifiers of a row block whose LA driver is selected are enabled and driven, then other LA drivers of conjunction areas positioned over and under the selected one are not driven when using the partial word line activation method. As a result, the reduction in the driving capacity as such may result in a decrease in the speed of sensing and active restoration of bit lines.
Even if the problems of decreasing the speed of sensing and active restoration processes can be solved by enlarging the size of PMOS and NMOS transistors of LA drivers, there may be another problem of increasing an area accommodating the layout structure of a device.
Therefore, an improved technique is desirable to secure the driving capacity of LA drivers without enlarging the size of driving transistors of LA drivers in a semiconductor memory device accessing in a partial word line activation method. In other words, it is desirable to develop a device that can reduce consumption of active power, secure the driving capacity of LA drivers and improve the speed of sensing and active restoration (re-writing of cell data) processes of memory cells, thereby making a progress in the performance of the semiconductor memory device.
Disclosed herein is a semiconductor memory device, comprising a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks; a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks; a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed, said conjunction areas comprising: one or more LA drivers adapted to drive block sense amplifiers; one or more PXiD circuits adapted to generate driving control signals to control sub-word line drivers; and one or more BSYD circuits adapted to selectively enables LA drivers in response to transmitted block control signals; and a plurality of block control units adapted to generate upper and lower block control signals by combining column and row block address decoding signals and simultaneously activating two or more BSYD circuits with the block control signals.
In another aspect of the invention, the block control unit generates upper and lower block control signals BSYou, BSYod and block control signals in combination with column block address decoding signals SY1-Sym, row address decoding LSB signals X0,X0#, and output signals BSYid, BSYiu of the block control unit.
In another aspect of the invention, the row address decoding LSB signal X0 is activated at the same time when odd word line driving signal PX1 or PX3 is activated, and the row address decoding LSB signal X0# is activated at the same time that even word line driving signals PX0 or PX2 is activated.
In another aspect of the invention, the level of the block control signal generated by the block control unit is a high level of voltage, VVP, higher than that of the normal supply voltage.
In another aspect of the invention, the LA drivers of a plurality of circuit blocks are arranged in each conjunction area.
In another aspect of the invention, the LA drivers in a plurality of circuit blocks are respectively arranged by two conjunction area.
In another aspect of the invention, all the block control signals BSYi respectively output from a plurality of block control units are set at the high level thereof during the refresh operations of the memory cells.
Disclosed is an embodiment of a semiconductor memory device, comprising a plurality of memory cell array blocks constructed with a plurality of refresh type memory cells; a refresh circuit adapted to generate refresh address signals to refresh the memory cells during a refresh operation; row and column decoders adapted to designate addresses to one or more memory cells according to address signals; a plurality of sub-word line drivers arranged at the memory cell array blocks in the first direction and shared by two memory cell array blocks; a plurality of block sense amplifiers arranged at the memory cell array blocks in the second direction, in perpendicular to that of the first one, and shared by two memory cell array blocks; a plurality of circuit blocks constructed with LA drivers respectively arranged at each conjunction area, where areas accommodating sub-word line drivers and block sense amplifiers are crossed, adapted to drive the block sense amplifiers, a PXiD circuit that generates driving control signals to control sub-word line drivers to activate sub-word lines connected with the memory cells; and a BSYD circuit adapted to selectively enable said LA drivers in response to transmitted block control signals; and a plurality of block control units arranged correspondingly to the number of circuit blocks and adapted to respectively generate upper and lower block control signals by combining column and row block address decoding signals and simultaneously activating two or more BSYD circuits of the circuit blocks.
In another aspect of this embodiment, the block control units further comprises a first NAND gate adapted to generate a NAND response by receiving one of row address decoding LSB signals X0,X0# and column block address decoding signals SYi; a second NAND gate adapted to generate a NAND response by receiving the rest of the row address decoding LSB signals X0,X0# and column block address decoding signals SYi; a NOR gate adapted to generate a NOR response by receiving the column block address decoding signals and output signals BSYid, BSYiu of the block control unit respectively positioned at top and bottom parts thereof; a first inverter adapted to invert an output of the first NAND gate and generate an upper block control signal BSYou; a second inverter adapted to invert an output of the second NAND gate and generate a lower block control signal BSYou; and a third inverter adapted to invert an output of the NOR gate and generate a block control signal BSYi.
In another aspect of the embodiment, the BSYD circuit comprises a first inverter adapted to invert the block control signals; a second inverter adapted to invert an output of the first inverter; a NAND gate adapted to receive an output of the second inverter and the first drive enable signal and outputting a result of NAND gating them as a first driver activation control signal; and a NOR gate 104 adapted to receive an output of the first inverter and the second activation enable signal and outputting a result of NOR gating them as a second drive activation control signal.
In another aspect of the embodiment the PXiD circuit comprises a first NAND gate adapted to receive address coding LSB signals PXi and the block control signals to generate a NAND response; a second NAND gate adapted to receive address coding LSB signals PXi and the block control signals to generate a NAND response; a first inverter operated by a high level of voltage adapted to invert an output of the first NAND gate and generating the first driving control signal to control the sub-word line drivers; and a second inverter adapted to invert an output of the second NAND gate and generating the second driving control signal PXiDD to control the sub-word line driver.
In another aspect of the embodiment, the LA drivers comprise a PMOS transistor with its source being connected with a node where cell array supply voltage is supplied, its gate to receive the first driver activation control signal and its drain to output a first block sense amplifier activation signal; a NMOS transistor with its source being connected to a node where supply voltage is provided, its gate to receive the second driver activation control signal and its drain to output the second block sense amplifier activation signal; the first and second NMOS transistors with its drain-source channel being connected between drains of the PMOS and NMOS transistors and all gates to commonly receive an equalize signal; and an equalizing NMOS transistor with its gate to receive the equalizing signal and its drain-source channel being connected between the drains of the PMOS and NMOS transistor.
In another aspect of the embodiment, the BSYD circuit comprises a first inverter adapted to invert the block control signals; a second inverter adapted to invert an output of the first inverter; a NAND gate adapted to receive an output of the second inverter and the first drive enable signal and outputting a result of NAND gating them as a first driver activation control signal; and a NOR gate 104 adapted to receive an output of the first inverter and the second activation enable signal and outputting a result of NOR gating them as a second drive activation control signal.
Also disclosed is a method of operating a semiconductor memory device, comprising combining column block address decoding signals and row address decoding LSB signals; and activating with a combined signals respectively two BSYD circuits that drive LA drivers arranged in conjunction areas.
In another aspect of the method, 4 LA drivers are driven to drive two block sense amplifiers when two BSYD circuits are activated.
In another aspect of the method, sensing and active restoration processes are performed to non-selected column memory cell array blocks that commonly share word lines of selected column memory cell array blocks as well as the column memory cell array blocks selected when two BSYD circuits are activated.
Disclosed is a semiconductor memory device, comprising a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks; a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks; a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed, said conjunction areas comprising: one or more LA driver means for driving said block sense amplifiers; one or more PXiD circuit means for generating driving control signals to control sub-word line drivers; and one or more BSYD circuit means for selectively enabling LA drivers in response to transmitted block control signals; and a plurality of block control unit means for generating upper and lower block control signals.